1. Field of the Invention
The present invention is generally related to methods for treating semiconductor processing components for use in a semiconductor fabrication environment, as well as semiconductor processing components formed thereby.
2. Description of the Related Art
In the art of semiconductor processing, typically integrated circuit devices are formed through various wafer processing techniques, in which semiconductor (principally silicon) wafers are processed through various stations or tools. Processing operations include, for example, high temperature diffusion, thermal processing, ion implant, annealing, photolithography, polishing, deposition, etc. As new generation semiconductor devices are developed, there is an intense demand in the industry to achieve better and better purity levels during such processing operations. In addition, there continues to be an intense driving force in transitioning to larger and larger semiconductor wafers. Currently, the semiconductor industry is undergoing a transition from 200 mm to 300 mm wafers. The desire for superior purity levels and larger wafers introduces further integration challenges for next generation processing.
In this context, it has been found that as wafer size increases, the gravitational stresses caused by the increased mass of the wafers and increased surface area, cause what is understood as crystallographic slip in the semiconductor wafer. Crystallographic slip manifests itself as slip lines in the wafer which cause a decrease in device yield proportional with an increase in wafer size, and undermine some of the cost advantages associated with larger surface area wafers.
In an attempt to minimize crystallographic slip, wafers need to be more fully supported during processing operations. One technique is to machine the semiconductor processing components to provide a smooth finish particularly along those portions of the processing component that contact the wafer. Such processing components include semiconductor wafer jigs, horizontal and vertical wafer boats, and wafer carriers, for example. Typically, the improved surface finish can be accomplished by machining slots into a wafer carrier or jig. While appropriate surface finishes may be engineered into the semiconductor processing component utilizing existing technology, additional issues have arisen, and in particular, a decrease in purity and attendant increase in contamination of the processing component.
U.S. Pat. No. 6,093,644 discloses a process in which an oxidation step is carried out, followed by oxide layer removal. However, the techniques disclosed therein do not adequately address certain contamination issues, and appear to focus on global impurity levels of the component, and not impurity levels along critical portions of the component.
Despite improvements in the industry to address next generation purity concerns as well as handling issues associated with larger-sized semiconductor wafers, a need continues to exist in the art for further improved semiconductor processing components, methods for forming such components, and methods for processing semiconductor wafers.